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ISBN-10: 0738135011

ISBN-13: 9780738135014

Average syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this typical.

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5 Use of constant functions Supported. 9 Disabling of named blocks and tasks disable_statement ::= disable hierarchical_task_identifier ; | disable hierarchical_block_identifier ; The block identifier shall be that of the enclosing block. Disable of any other blocks shall not be supported. 1 Modules module_declaration ::= { attribute_instance } module_keyword module_identifier [ module_parameter_port_list ] [ list_of_ports ] ; { module_item } endmodule | { attribute_instance } module_keyword module_identifier [ module_parameter_port_list ] [ list_of_port_declarations ] ; { non_port_module_item } endmodule module_keyword ::= module | macromodule module_parameter_port_list ::= # ( parameter_declaration { , parameter_declaration } ) Copyright © 2002 IEEE.

The internals of the instance or the module shall not be subject to optimization. Similarly, a net with such an attribute shall be preserved. If a reg has a keep attribute and an fsm_state attribute, the fsm_state attribute shall be ignored. This attribute does not apply if the reg with the fsm_state attribute, has not been inferred as an edge-sensitive storage device. overflow(nextstage)); keep *) reg [3:0] count_state; keep *) wire [7:0] outa; // default keep is keep = 1. (* synthesis, keep *) reg [7:0] b; (* synthesis, keep = 1 *) my_design my_design1 (out1, in1, clkin); // Preserve the instance and its subelements from optimization.

1-2002 IEEE STANDARD FOR VERILOG® NOTE—This macro definition makes it possible for Verilog users to add conditionally compiled code to their design that will be read and interpreted by synthesis tools but that by default will be ignored by simulators (unless the Verilog simulation input stream also defines the SYNTHESIS text macro). we(we)); `endif endmodule NOTE—The use of the above conditional compilation capability removes the need to use the deprecated translate_off/ translate_on synthesis pragmas.

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1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis


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